Design Solutions For Modular Satellite Architectures

The cost-effective access to space envisaged by ESA would open a wide range of new opportunities and markets, but is still many years ahead. There is still a lack of devices, circuits, systems which make possible to develop satellites, ground stations and related services at costs compatible with the budget of academic institutions and small and medium enterprises (SMEs). As soon as the development time and cost of small satellites will fall below a certain threshold (e.g. 100,000 to 500,000 €), appropriate business models will likely develop to ensure a cost-effective and pervasive access to space, and related infrastructures and services. These considerations spurred the activity described in this paper, which is aimed at: - proving the feasibility of low-cost satellites using COTS (Commercial Off The Shelf) devices. This is a new trend in the space industry, which is not yet fully exploited due to the belief that COTS devices are not reliable enough for this kind of applications; - developing a flight model of a flexible and reliable nano-satellite with less than 25,000€; - training students in the field of avionics space systems: the design here described is developed by a team including undergraduate students working towards their graduation work. The educational aspects include the development of specific new university courses; - developing expertise in the field of low-cost avionic systems, both internally (university staff) and externally (graduated students will bring their expertise in their future work activity); - gather and cluster expertise and resources available inside the university around a common high-tech project; - creating a working group composed of both University and SMEs devoted to the application of commercially available technology to space environment. The first step in this direction was the development of a small low cost nano-satellite, started in the year 2004: the name of this project was PiCPoT (Piccolo Cubo del Politecnico di Torino, Small Cube of Politecnico di Torino). The project was carried out by some departments of the Politecnico, in particular Electronics and Aerospace. The main goal of the project was to evaluate the feasibility of using COTS components in a space project in order to greatly reduce costs; the design exploited internal subsystems modularity to allow reuse and further cost reduction for future missions. Starting from the PiCPoT experience, in 2006 we began a new project called ARaMiS (Speretta et al., 2007) which is the Italian acronym for Modular Architecture for Satellites. This work describes how the architecture of the ARaMiS satellite has been obtained from the lesson learned from our former experience. Moreover we describe satellite operations, giving some details of the major subsystems. This work is composed of two parts. The first one describes the design methodology, solutions and techniques that we used to develop the PiCPoT satellite; it gives an overview of its operations, with some details of the major subsystems. Details on the specifications can also be found in (Del Corso et al., 2007; Passerone et al, 2008). The second part, indeed exploits the experience achieved during the PiCPoT development and describes a proposal for a low-cost modular architecture for satellite

Development of a payload for the characterization of fram microcontrollers to radiations

The space radiation environment can have serious effects on spacecraft electronics. The effect of incoming cosmic rays of galactic, solar origin and their interaction with the Earth's magnetic field limit system endurance and reliability. Transient effects from individual high-energy protons or heavy ions can in fact disrupt system operation irreversibly causing system faults that can be very dangerous. To test radiation effects on COTS FRAM-microcontrollers, we created a payload tile for the AraMIS-C1 structure (modular architecture for small satellites, developed by Politecnico di Torino) called 1B521 Radiation Characterization Payload. The satellite that includes this payload will be launched in a LEO (Low Earth Orbit) approximately between 600-800 km distance from the Earth. Spacecraft systems operating in this area must be hardened to withstand the radiation environment, and the electronics must be designed with several layers of redundancy. The damages produced by radiations are the cumulative effects of the dose received (TID) that can cause functional failures, and the effects of a single particle hit (SEE) that mainly cause single event upset (SEU) and single event latch-up (SEL). Finding SEU and SEL sensitivity of the microcontroller is the main goal of the mission. FRAM (ferroelectric memories) cells store the information as a PZT film polarization and a charged particle hit has a very small possibility to cause a change in the polarization. The ferroelectric dielectric leads to a different behaviour of the cell compared with a DRAM one, producing many advantages especially for what concerns the overall power consumption in read/write cycles and the non-volatility properties of the device. The problems due to ionizing radiation are in our opinion concentrated in the CMOS logic surrounding the memory array. Our payload is hosted in a board included in a 1U Cubesat satellite. The board presents two identical microcontrollers MSP430FR6989 (Texas Instruments) that run the same program, but one uses software hardening techniques that should prevent malfunctions due to transient errors like SEUs and SEFI. We also monitor SELs and when such an event is detected the system will power cycle the payload to prevent physical damage. The on-board computer of the satellite monitors the behaviour of the payload, logging any malfunctioning and creating an error report. We are waiting for a launch opportunity to get live data and verify our assumption that FRAM based microcontrollers can be extremely useful in low cost university satellites and to test the effectiveness of software hardening

Enhancement of a 2D array processor for an efficient implementation of visual perception tasks

The low-level processing of images is generally a heavy step in vision applications, because the computations, even if very simple, must be iterated for every pixel in the image. Nevertheless, sometimes the processing has a different relevance for different image areas. This fact allows to decrease the number of computations, skipping the pixels which would not produce significant results, and implementing a sort of multiple focus of attention. The authors present a hardware extension devoted to the implementation of a data-driven focus of attention on PAPRICA architecture, but can be applied to any SIMD array processor using the same processor virtualization mechanism as PAPRICA. The focus of attention mechanism can be used both to implement different elaborations on different image areas, and to skip the elaboration where it is useless, improving the performances with respect to a traditional architecture

Signal integrity: An interactive multimedia course

The main bottleneck in high speed digital processing systems comes interconnections. An understanding of the "signal integrity" problems is mandatory for digital systems designer, but requires familiarity with the analog and high frequency domains. A CD-ROM on Electromagnetic Compatibility with a section on signal integrity attempts to bridge the gap, by providing an application-oriented description of problems and solutions, with extensive use of interactive multimedia